- #Fpga rf communications library labview 2013 driver#
- #Fpga rf communications library labview 2013 upgrade#
- #Fpga rf communications library labview 2013 software#
Both experiments require 53 MHz batches of 8 GeV protons to be re-bunched into 150 ns, 2.5 MHz pulses for extraction to the g-2 target for Muon g-2 and to a delivery ring with a single RF cavity running at 2.36 MHz for Mu2e. The Mu2e experiment measures the conversion rate of muons into electrons and the Muon g-2 experiment measures the muon magnetic moment. LLRF System for the Fermilab Muon g-2 and Mu2e Projects The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.« less The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more.
#Fpga rf communications library labview 2013 upgrade#
For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array ( FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overallmore » LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. In addition, the purpose of this system is to control a 500 MHz RF cavity, so the system will be applied to the superconducting cavity to be installed in the PLS storage ring, and its performance will be tested.Ī bunch to bucket phase detector for the RHIC LLRF upgrade platformĪs part of the overall development effort for the RHIC LLRF Upgrade Platform, a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The control algorithms will be implemented by using the VHDL (VHSIC (very high speed integrated circuits) hardware description language), and the EPICS (experiment physics and industrial control system) will be ported to the host computer for the communication. The proposed LLRF control system includes an analog front-end, a digital board (ADC (analog to digital converter), DAC (digital to analog converter), FPGA, etc.) and a RF & clock generation system. This paper describes the design of the FPGA (field programmable gate array) based LLRF control system and the status of development for this system. The digital LLRF control system has advantages related with flexibility and fast reconfiguration. For this reason, many accelerator laboratories have completed or are completing the developments of digital LLRF control systems. Recent advances in digital signal processors and data acquisition systems have allowed the LLRF control system to be implemented in digitally and have made it possible to meet the higher demands associated with the performance of LLRF control systems, such as stability, accuracy, etc. The LLRF (low-level radio-frequency) control system which regulates the amplitude and the phase of the accelerating voltage inside a RF cavity is essential to ensure the stable operation of charged particle accelerators.
#Fpga rf communications library labview 2013 driver#
Similarly, programs compiled with this version of the driver will not be compatible with older versions of the IVI-C driver.Design and development progress of a LLRF control system for a 500 MHz superconducting cavity Programs using the C/C++ IVI-C driver must be recompiled for this version of the driver. Note: This release is not binary compatible with prior releases of the IVI-C driver. Fixed issue causing a ReadIQData() exception after running an IF Flatness alignment.
#Fpga rf communications library labview 2013 software#
M9300A FPGA 1.0.1.0 available – Optional, not currently required for any new software features. M9214A FPGA 1.0.2.3 available – Optional, not currently required for any new software features. All functionality is now accessed directly via the AgM9391 Previous 1.1.300.0 release offered multi-channel support via 89600 VSA software only. Added MultiChannelSync IVI interface and MultiChannel C# example to allow direct utilization of multi-channel capability. Added support for 89600 VSA Software stepped spectrum measurement (Option 89601B-SSA).